1. Field of the Invention
The present invention relates to a pulse width adjusting circuit and a pulse width adjusting method for outputting an output signal generated by adjusting a pulse width of an input pulse signal. This patent application incorporates herein by reference the contents of a Japanese Patent Application No. 2004-011412 filed on Jan. 20, 2004, if applicable.
2. Related Art
FIG. 1 shows a publicly-known conventional pulse width adjusting circuit 300, which is a circuit for adjusting a pulse width of an input pulse signal. In the pulse width adjusting circuit 300, an adjusting section 302 adjusts the pulse width. The adjusting section 302 includes a variable delay circuit 304 and an AND circuit 306, to generate a pulse signal having a pulse width corresponding to the delay time achieved by the variable delay circuit 304 by performing a logical AND operation between an inverse signal of the input pulse signal and the pulse signal which has been delayed by the variable delay circuit 304 (see Patent Document 1, for example). The pulse signal generated by the adjusting section 302 is delayed by a desired time by the delay circuit 308, to be output to an external device.
In addition, the pulse width adjusting circuit 300 has a function of measuring the pulse width of the pulse signal generated by the adjusting section 302. To perform such measurement, a pulse is generated by using as a reference the falling edge of the pulse signal generated by the adjusting section 302 in the pulse width adjusting circuit 300, and the generated pulse is fed back into the adjusting section 302, so that a loop is formed. Subsequently, the cycle of the formed loop is calculated by using a counter 316. After this, a pulse is generated by using as a reference the rising edge of the pulse signal generated by the adjusting section 302 in the pulse width adjusting circuit 300, and the generated pulse is fed back into the adjusting section 302, so that a loop is formed. The cycle of the formed loop is then similarly calculated by using the counter 316. By calculating the difference between these cycles, the pulse width adjusting circuit 300 obtains the pulse width of the pulse signal generated by the adjusting section 302.
FIG. 2 illustrates the pulse width measuring operation performed by the conventional pulse width adjusting circuit 300. FIG. 2A illustrates the operation performed when the pulse generated by using as a reference the rising edge of the pulse signal is fed back, and FIG. 2B illustrates the operation performed when the pulse generated by using as a reference the rising edge of the pulse signal is fed back. Referring to FIG. 2A, the input pulse is input into the adjusting section 302. The AND circuit 306 subsequently outputs the pulse signal generated by adjusting the pulse width of the input pulse to P1. The delay circuit 308 delays the pulse signal, and outputs the delayed pulse signal. Here, the delay time with respect to the rising edge of the pulse signal is Tpd1, and the delay time with respect to the falling edge is Tpd1′, where Tpd1 and Tpd1′ are different from each other.
An XOR circuit 310 inverses and outputs the pulse signal. Here, the XOR circuit 310 also delays the pulse signal. Similarly to the case of the delay circuit 308, the delay time with respect to the rising edge of the pulse signal is Tpd2, and the delay time with respect to the falling edge is Tpd2′, where Tpd2 and Tpd2′ are different from each other.
A differentiating circuit 312 generates a pulse signal having a pulse width of P2 by using as a reference the falling edge of the pulse signal received from the XOR circuit 310. The integrating circuit 314 adjusts the pulse width of the pulse signal received from the differentiating circuit 312 to P2+P3, and outputs the adjusted pulse signal. It should be noted that the pulse width of P2+P3 is equal to the pulse width of the input pulse which is originally supplied to the pulse width adjusting section 302. The integrating circuit 314 supplies the pulse signal having the adjusted pulse width to the pulse width adjusting section 302, so that the pulse signal is looped. Here, the cycle T1 of this loop is represented by the following expression.T1=Tpd1+Tpd2+P2+P3
The following explains the operation performed when the pulse generated by using as a reference the falling edge of the pulse signal is fed back. As shown in FIG. 2B, the XOR circuit 310 outputs the received pulse signal without inverting. The differentiating circuit 312 subsequently generates a pulse signal having a pulse width of P2 by using as a reference the falling edge of the pulse signal received from the XOR circuit 310. The integrating circuit 314 generates and loops a pulse signal having a pulse width of P2+P3. Here, the cycle T2 of this loop is represented by the following expression.T2=P1+Tpd1′+Tpd2′+P2+P3
The difference between the cycles T2 and T1 is represented as follows.T2−T1=P1+(Tpd1′−Tpd1)+(Tpd2′−Tpd2)In the conventional pulse width adjusting circuit 300, this difference is treated as the pulse width of the pulse generated by the pulse width adjusting section 302. If Tpd1′=Tpd1 and Tpd2′=Tpd2 are satisfied, the difference precisely denotes the pulse width P1. However, the pulse width calculated in the above-described manner has a margin of error because the delay times, created by each of the delay circuit 308 and XOR circuit 310, with respect to the rising and falling edges are different from each other. This makes it difficult to measure an accurate pulse width of the pulse signal generated by the pulse width adjusting section 302. As a result, adjustment of the pulse width can not be accurate. In addition to this problem, the conventional pulse width adjusting circuit 300 also has a problem in relation to an offset delay time of the variable delay circuit 304.
FIG. 3 illustrates the configuration of the variable delay circuit 304. The variable delay circuit 304 includes a large delay circuit section 318 and a small delay circuit section 305. The small delay circuit section 305 generates a delay in smaller steps than the large delay circuit section 318. The large delay circuit section 318 and the small delay circuit section 305 are connected to each other in series. The variable delay circuit 304 delays the pulse signal by a time equal to the sum of the delay time achieved by the large delay circuit section 318 and the delay time achieved by the small delay circuit section 305.
The large delay circuit section 318 is configured, for example, in such a manner that a plurality of sequences each consisting of a plurality of inverters connected in series are connected in parallel. The delay time created by the large delay circuit section 318 is controlled by selecting the number of inverter sequences through which the pulse signal passes. On the other hand, the small delay circuit section 305 is configured in such a manner that a plurality of delay elements each constituted by two inverters and a variable capacity element are connected to each other in series. The delay time created by the small delay circuit section 305 is controlled by varying the capacity of each variable capacity element. The maximum delay time which can be achieved by the small delay circuit section 305 is equal to the delay resolution of the large delay circuit section 318. The variable delay circuit 304 having the above-described configuration provides a highly variable delay time, a high delay resolution and a small delay-setting step.
In the small delay circuit section 305, the pulse signal passes through the inverters connected in series. Therefore, a predetermined amount of offset delay unavoidably occurs even when the delay time is set shortest. Such offset delay can be reduced by using a smaller number of combinations of the inverters and variable capacity element. However, to keep the delay time created by the small delay circuit section 305 within the range of the delay resolution of the large delay circuit section 318, the small delay circuit section 305 needs around five or six combinations of the inverters and variable capacity element. Accordingly, it is difficult to reduce the offset delay of the small delay circuit section 305. For the reasons stated above, the conventional pulse width adjusting circuit 300 has difficulties in simultaneously realizing generation of a pulse signal having a small pulse width and adjustment of a pulse width with high resolution.                [Patent Document 1] Unexamined Japanese Patent Application Publication No. 1998-303709        
As explained above, a conventional pulse width adjusting circuit has difficulties in simultaneously realizing generation of a pulse signal having a small pulse width and adjustment of a pulse width with high resolution. Also, the conventional pulse width adjusting circuit can not measure an accurate pulse width of the pulse signal generated, which makes it difficult to adjust the pulse width accurately.